Section: Partnerships and Cooperations

European Initiatives

DAL: ERC AdG 2010- 267175, 04-2011/03-2016

Participants : Pierre Michaud, Luis Germán García Morales, Nathanaël Prémillieu, Erven Rohou, André Seznec, Bharath Narasimha Swamy, Ricardo Andrés Velásquez, Arthur Pérais, Surya Narayanan, Arjun Suresh, Sajith Kalathingal, Kamil Kedzierski.

In the DAL, Defying Amdahl's Law project, we envision that, around 2020, the processor chips will feature a few complex cores and many (may be 1000s) simpler, more silicon and power effective cores. In the DAL research project, we will explore the microarchitecture techniques that will be needed to enable high performance on such heterogeneous processor chips. Very high performance will be required on both sequential sections —legacy sequential codes, sequential sections of parallel applications— and critical threads on parallel applications —e.g. the main thread controlling the application. Our research will focus on enhancing single process performance. On the microarchitecture side, we will explore both a radically new approach, the sequential accelerator, and more conventional processor architectures. We will also study how to exploit heterogeneous multicore architectures to enhance sequential thread performance.

For more information, see http://www.irisa.fr/alf/dal .

HiPEAC3 NoE

Participants : François Bodin, Pierre Michaud, Erven Rohou, André Seznec.

F. Bodin, P. Michaud, A. Seznec and E. Rohou are members of the European Network of Excellence HiPEAC3. HiPEAC3 addresses the design and implementation of high-performance commodity computing devices in the 10+ year horizon, covering both the processor design, the optimizing compiler infrastructure, and the evaluation of upcoming applications made possible by the increased computing power of future devices.

COST Action TACLe - Timing Analysis on Code-Level 10-2012/09-2015

Participants : Damien Hardy, Isabelle Puaut.

Embedded systems increasingly permeate our daily lives. Many of those systems are business- or safety-critical, with strict timing requirements. Code-level timing analysis is indispensable to ascertain whether these requirements are met. However, recent developments in hardware, especially multicore processors, and software organization make the analysis increasingly harder, thus challenging the evolution of timing analysis techniques. Principles for building "timing-composable" embedded systems are needed to make timing analysis tractable in the future. The furthering and consolidation of those principles require increased contacts within the timing analysis community as well as with the neighboring communities that deal with other forms of analysis, such as model checking and type inference, and with computer architectures and compilers. The goal of this COST Action (http://www.cost.eu/domains_actions/ict/Actions/IC1202 ) is to gather these forces in order to develop industrial strength code-level timing analysis techniques for future generation embedded systems.

Twelve countries are currently involved in this COST action.